Bài giảng Spartan-IIE Technical Details Table of Contents

st use the same voltage sourceAll VCCO pins in a bank must be tied to the same voltageOnly one VCCO voltage for smaller pin count packagesTQ144, PQ208Outputs not requiring VCCO fit in the bankGTL, GTL+Configuration pins need special considerationConfiguration pins are located on the right side of device in Banks 2 and 3VCCO must be 3.3 volts for serial PROMs configurationFor Academic Use OnlyFor Academic Use OnlySingle-Ended I/O Standards BenefitsReduced EMI compared to 3.3V TTLLow Output Voltage SwingSlow Edge Rates (dV/dt)Reduced Power ConsumptionReduced Noise With External TerminationReduced reflectionRingingCross-talkHigher Performance/Higher BandwidthFor Academic Use OnlyFor Academic Use OnlyDifferential I/O BenefitsI/O ConnectivitySignificant Cost SavingsReduced EMIFewer pinsFewer PCB layers, fewer PCB traces (PCB area savings)Fewer/smaller connectorsNo external transceiversHigh performance per pin pair - up to 400 Mb/secReduced EMI due to low output voltage swingHigh noise immunityReduced power consumptionSpartan-IIE Supports LVDS, Bus LVDS, and LVPECLFor Academic Use OnlyFor Academic Use OnlyLVDSLVDSLVDSLVDSLVPECLLVPECLLVPECLLVPECLSelectI/O: Differential I/ODifferential I/O is a standard featureSupported in all devices densities, all speed gradesMore differential I/Os within a deviceUp to 240 I/O pairsOffers flexibility in board layout Flexible differential I/OsUse any I/O as input, output or bi-directionalSpartan-IIECan be driven by any standard LVDS/LVPECL driverComplies with LVDS/LVPECL receiver specsFor Academic Use OnlyFor Academic Use OnlySelectI/O: Differential I/O Configurations Point to PointOne transmitter and one receiverMostly used by LVDS/LVPECL in chip-to-chip applicationsMulti-DropOne transmitter and multiple receiversUsed by Bus LVDS/LVPECL in backplane applicationsMulti-pointMultiple transceiversUsed by Bus LVDS/LVPECL in backplane applicationsMulti-dropPoint to PointMulti-PointFor Academic Use OnlyFor Academic Use OnlySelectI/O: LVDS & LVPECLAll I/Os have LVDS/LVPECL capabilityDifferential signal pairs can be used asSynchronous inputs or outputsAsynchronous inputsSome as asynchronous outputsSynchronousSignal comes from IOB flip-flopAsynchronousSignal comes from internal logicFor Academic Use OnlyFor Academic Use OnlyLVDS - Low Voltage Differential SignalingLVDS is a differential signaling interconnect technologyRequires two pins per channelLVDS was first used as a interconnectivity technology in laptops and displays to alleviate EMI issuesTechnology is now widely usedA broad spectrum of telecom and networking applicationsMainstream consumer applications like digital video and displaysAnil Telikepalli:OrganizeWhat is LVDS?For Academic Use OnlyFor Academic Use OnlyLVDS BenefitsHigher I/O speedLower costSerialize multiple single-ended to differential channel signalsSave I/O pinsUse a smaller packageSave board spaceTechnology and process independentEasy migration path for lower supply voltagesMaintain same signal levelsMaintain same performanceLow powerLow noiseLow EMIFor Academic Use OnlyFor Academic Use OnlyLVDS Low Power AdvantageLVDS technology saves power in several important waysPower dissipation at the terminator is ~1.2 mWRS-422 driver delivers 3 V across a termination of 100 , for 90 mW power consumption... 75 times more than LVDS!Due to the current mode driver design, the frequency component of ICC is greatly reducedCompared to TTL/CMOS transceivers where the dynamic power consumption increases exponentially with frequencyFor Academic Use OnlyFor Academic Use OnlyLVDS Noise Immunity AdvantageROUT is clean even in cases of extreme common mode noise contaminationFor Academic Use OnlyFor Academic Use OnlyLVDS benefits - Low EMILow voltage swing (~350mV)Slow edge rates compared to other technologies (1V/ns)Current mode of operation ensures low ICC spikes High noise immunitySwitching noise cancels between the two linesData is not effected by the noiseExternal noise effects both lines, but the voltage difference stays about the sameFor Academic Use OnlyFor Academic Use OnlyLVDS ApplicationsCommunications and NetworkingSwitchesRepeatersWireless base stationsData CommunicationsRoutersHubsFor Academic Use OnlyFor Academic Use OnlyLVDS Applications (cont’d)Consumer ElectronicsDigital camerasFlat panel displaysOffice/HomePrintersCopiersVarious backplane applicationsFor Academic Use OnlyFor Academic Use OnlySpartan-IIE LVDS Benefits Exceptional performanceUp to 400Mb/sec. per differential pair Significant Cost SavingsReduced EMIFewer pins (smaller package)Fewer PCB layersFewer PCB traces (PCB area savings)Fewer/smaller connectorsNo transceiversQuicker Time-to-marketFewer EMI issuesFor Academic Use OnlyFor Academic Use OnlyLVDS Driver and ReceiverDriverReceiverSpartan-IIEFPGASpartan-IIEFPGAFor Academic Use OnlyFor Academic Use OnlySelectI/O: Bus LVDSAll I/Os have Bus LVDS capabilityFully compatible with industry-standard Bus LVDS devices from National Semiconductor and other vendorsFor Academic Use OnlyFor Academic Use Only4 Gb/s4 Gb/s40 Pins @ 100MHzSingle-ended I/OLVDS I/O40 Pins@ 100MHz20 Pins @ 400Mbps20 Pins @ 400Mbps# of Pins: 80# of Pins: 468 Gb/s Switch8 Gb/s Switch8 Gb/s SwitchExample1 clock pair per8 data line pairs = 6 pins1 clock pair per8 data line pairs = 6 pinsLVDS Benefits – Reduced I/O CountFor Academic Use OnlyFor Academic Use OnlyLVDS Clock SourceLVDS ClockDistributor222Spartan-IIE 1Spartan-IIE nSpartan-IIE 22No LVDS-TTL TranslatorEqual-Length Point-to-Point LVDS PCB Clock TracesSpartan-IIE LVDS ExampleClock DistributionClock speeds of 200 MHz+ can be distributed with ease using LVDSSpartan-IIE Eliminates LVDS-to-TTL Converters -- Eliminates 2ns Delay & SkewBenefits - Higher performance, low EMI, lower cost, fewer componentsFor Academic Use OnlyFor Academic Use OnlyExternalRAMExternalRAMZero-Delay Local Clock Generation to Any of Spartan-IIE I/O StandardsSSTLTTLDLLDLLSpartan-IIELVDS ClockBenefits - Low EMI, lower cost, fewer componentsSpartan-IIE LVDS ExampleClock Conversion with Zero DelayFor Academic Use OnlyFor Academic Use OnlyLVPECL BenefitsHigher I/O speedBoard-level clock distributionZero-delay conversion of LVPECL clocks into virtually any other I/O standardLower costSerialize multiple single-ended to differential channel signalsSave I/O pinsUse a smaller packageSave board spaceLow powerLow noiseLow EMIFor Academic Use OnlyFor Academic Use OnlyLVPECL ApplicationsBackplanesHigh performance clocking100 MHz and aboveOptical TransceiverHigh speed networkingMixed-signal interfacingFor Academic Use OnlyFor Academic Use OnlyLVPECL Driver and ReceiverDriverReceiverSpartan-IIEFPGASpartan-IIEFPGAFor Academic Use OnlyFor Academic Use OnlyLVPECL: Clock ConversionReceive and convert high speed clocks with zero delayZero-delay clock generation to any of SelectI/O StandardsEliminate costly bus translatorsExternalRAMSSTLTTLOtherDeviceLVPECLClock SourceDLLDLLPECL-to-TTLconverterPECL-to-TTLconverterFor Academic Use OnlyFor Academic Use OnlyConfiguration MethodsMaster serial modeSlave serial modeSlave parallel modeJTAG modeIRLMultiple devices can be daisy-chained inMaster serial modeSlave serial modeJTAG modeMultiLINXJTAGTarget BoardFor Academic Use OnlyFor Academic Use OnlyMaster Serial ModeSpartan-IIE device acts like a masterGenerates configuration clock (CCLK) using internal oscillatorPROM stores the configuration dataConfiguration rate selectable from 4-60 MHz-30% to +45% variance due to process dependenceFor Academic Use OnlyFor Academic Use OnlySlave Serial ModeSpartan-IIE device acts like a slaveAn external clock source drives the CCLK pinConfiguration data is stored in PROM, flash, micro- controller or microprocessor memoryMaximum configuration rate of 66 MHzFor Academic Use OnlyFor Academic Use OnlySlave Parallel ModeSingle or multiple Spartan-IIE devices connected in parallelFor Academic Use OnlyFor Academic Use OnlySlave Parallel Mode (cont’d)Spartan-IIE device acts like a slaveAn external clock source drives the CCLK pinMicroprocessor, Microcontroller or CPLD controls configurationConfiguration data is stored in parallel PROM, flash, Microcontroller or Microprocessor memory Fastest configuration mode8 bits per CCLK cycle50MHz configuration rate (400 Mbit/sec)Supports ReadbackBi-directional read/write port for configuration and readbackFor Academic Use OnlyFor Academic Use OnlyIRL and Xilinx OnlineInternet Reconfigurable Logic (IRL)IRL is a design methodology to create field upgradable applicationsSupported by products, design guidelines and reference designsXilinx OnlineXilinx program to enable, identify and promote field upgradable applicationsFor Academic Use OnlyFor Academic Use Only4 main elements in IRL modelHost / ServerNetwork Target to be updatedPayload(s)Xilinx provides an API (PAVE) and a set of design guidelines that define how remote devices can be upgraded via a network. YourNetworkPAVEPayloadHostTargetIRL Methodology ElementsPortalServerPAVEPAVEFor Academic Use OnlyFor Academic Use OnlyPAVE FeaturesConfigures FPGAs / CPLDsIEEE 1149.1 JTAG / SelectMAP PAVE Payload upgrades PLD + system softwareSystems Integration Framework (SIF) within Wind River’s Tornado® environmentPAVE source distributed and supported by XilinxC++ / C ApplicationPlatform Abstraction Layer (PAL)VxWorks RTOSBSP for WRS VxWorks RTOSMicroprocessorPAVEDevice APIFPGAFor Academic Use OnlyFor Academic Use OnlyMultiLINX™ CableConfiguration and Readback supportUsing boundary scan (JTAG) modeSlave serial/parallel modeSupports USB interface on PCFastest configurationBaud rate up to 12MSupports RS-232 interface on PC and UNIXBaud rateUp to 57.6K on PCUp to 38.4K on UNIXFor Academic Use OnlyFor Academic Use OnlyMultiLINX CableFor Academic Use OnlyFor Academic Use OnlyParallel CableConfiguration and Readback supportUsing boundary scan (JTAG) modeSupports parallel port on PCBaud rate up to 57.6KFor Academic Use OnlyFor Academic Use OnlyParallel CableFor Academic Use OnlyFor Academic Use Only