Bài giảng Computer memory - Introduction - Memory Hierachy

COMPUTER MEMORY (DTV340) I. INTRODUCTION – MEMORY HIERARCHY 	University of Science Faculty of Electronics and TelecommunicationMemory DescriptionCapacity of a memory is described as # addresses x Word sizeMemory# of addr# of data lines# of addr lines# of total bytes1M x 81,048,5768201 MB2M x 42,097,1524211 MB1K x 41024410512 B4M x 324,194,304322216 MB16K x 6416,3846414128 KBEndianessBig EndianMost significant byte of a multi-byte word is stored at the lowest memory address e.g. Sun Sparc, PowerPCLittle Endian Least significant byte of a multi-byte word is stored at the lowest memory addresse.g. Intel x86Some embedded & DSP processors would support both for interoperabilityEndianessMost modern computers are byte addressable.2k4-2k3-2k2-2k1-2k4-01234567 04Byte address(a) Big-endian assignmentWordaddress•••2k4-2k3-2k2-2k1-2k4-124567 04Byte address(a) Little-endian assignment•••03Store0x00010203Memory Hierarchy The memory unit is an essential component in any digital computer since it is needed for storing programs and dataNot all accumulated information is needed by the CPU at the same timeTherefore, it is more economical to use low-cost storage devices to serve as a backup for storing the information that is not currently used by CPUMemory HierarchySince 1980, CPU has outpaced DRAMGap grew 50% per yearMemory HierarchyQ. How do architects address this gap? A. Put smaller, faster “cache” memories between CPU and DRAM. Create a “memory hierarchy”. Memory HierarchyThe memory unit that directly communicate with CPU is called the main memory Devices that provide backup storage are called auxiliary memory The memory hierarchy system consists of all storage devices employed in a computer system from the slow by high-capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster cache memoryMemory HierarchyThe main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through an I/O processorA special very-high-speed memory called cache is used to increase the speed of processing by making current programs and data available to the CPU at a rapid rateMemory HierarchyCPUCacheMain MemoryI/O ProcessorMagnetic DisksMemory HierarchyCPU logic is usually faster than main memory access time, with the result that processing speed is limited primarily by the speed of main memoryThe cache is used for storing segments of programs currently being executed in the CPU and temporary data frequently needed in the present calculations The typical access time ratio between cache and main memory is about 1 to 7~10 Auxiliary memory access time is usually 1000 times that of main memoryTypes of Internal memoriesMemory TypeCategoryErasureWrite MechanismVolatilityRAMRead-write memoryElectrically, byte-levelElectricallyVolatileROMRead-only memoryNot possibleMasksNonvolatilePROMElectricallyEPROMRead-mostly memoryUV light, chip-levelEEPROMElectrically, byte-levelFlash memoryElectrically, block-levelMain MemoryMost of the main memory in a general purpose computer is made up of RAM integrated circuits chipsRAM– Random Access memoryIntegrated RAM are available in two possible operating modes, Static and DynamicThe Block diagram of a RAM chip is shown next slides, the capacity of the memory is 128 words of 8 bits (one byte) per wordRandom-Access Memory (RAM)Static RAM (SRAM)Each cell stores bit with a six-transistor circuit.Retains value indefinitely, as long as it is kept powered.Relatively insensitive to disturbances such as electrical noise.Faster (8-16 times faster) and more expensive (8-16 times more expensive as well) than DRAM.Dynamic RAM (DRAM)Each cell stores bit with a capacitor and transistor.Value must be refreshed every 10-100 ms.Sensitive to disturbances.Slower and cheaper than SRAM.RAM ROMROM is used for storing programs that are PERMENTLY resident in the computer and for tables of constants that do not change in value once the production of the computer is completed The ROM portion of main memory is needed for storing an initial program called bootstrap loader, witch is to start the computer software operating when power is turned off ROMMemory Model Example32-bit address space can address up to 4GB (232) different memory locationsFlat Memory Model0x0A0xB60x410xFCLowerMemoryAddress0x00000000HigherMemoryAddress0x000000010x000000020x000000030xFFFFFFFF0x0DMemory Address MapMemory Address Map is a pictorial representation of assigned address space for each chip in the systemTo demonstrate an example, assume that a computer system needs 128 bytes of RAM and 512 bytes of ROMThe RAM have 128 byte and need seven address lines, where the ROM have 512 bytes and need 9 address linesMemory Address MapMemory Address MapThe hexadecimal address assigns a range of hexadecimal equivalent address for each chipLine 8 and 9 represent four distinct binary combination to specify which RAM we chose When line 10 is 0, CPU selects a RAM. And when it’s 1, it selects the ROMA19A18A17A01Mx4R/WCSA19A18A17A01Mx4R/WCS1-to-2DecoderCS 10D3D2D1D0Another Example Making a wider memoryHere is a 64K x 16 RAM, created from two 64K x 8 chips.The left chip contains the most significant 8 bits of the data.The right chip contains the lower 8 bits of the data.168888How to address memory1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit0123D7D6D5D4D3D2D1D04x8 Memory2-to-4DecoderCSChipSelect1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit0123D7D6D5D4D3D2D1D04x8 Memory2-to-4DecoderA0=1A1=0Access address = 0x1CSChipSelect=1How to address memoryUse 2 Decoders1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit01238x4 Memory2-to-4DecoderRowDecoderA1A21-to-2 Decoder Column DecoderD0D1D2D301CSChipSelectCSTri-stateBuffer (read)A0Tri-state BufferThe triangle represents a three-state buffer.Unlike regular logic gates, the output can be one of three different possibilities, as shown in the table.“Disconnected” means no output appears at all, in which case it’s safe to connect OUT to another output signal.The disconnected value is also sometimes called high impedance or Hi-Z.Bi-directional Bus using Tri-state BufferDirection(control data flow for read/write)ABInput/OutputRead/Write Memory1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit01238x4 Memory2-to-4RowDecoderA1A21-to-2 Column DecoderD0D1D2D301CSChipSelect = 0CSA0Rd/Wr = 0Read/Write Memory1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit1-bit01238x4 Memory2-to-4RowDecoderA1A21-to-2 Column DecoderD0D1D2D301CSChipSelect = 1CSRd/Wr = 1A0